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Creators/Authors contains: "Yang, Hoeseok"

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  1. ; ; (, IEEE)
    Full Text Available 
  2. ; ; ; ; ; (, 37th International Conference on VLSI Design)
    Accepted Manuscript Full Text Available
  3. ; ; ; (, 2021 IEEE International Symposium on Circuits and Systems (ISCAS))
    null (Ed.)
    Iterative computing, where the output accuracy gradually improves over multiple iterations, enables dynamic reconfiguration of energy-quality trade-offs by adjusting the latency (i.e., number of iterations). In order to take full advantage of the dynamic reconfigurability of iterative computing hardware, an efficient method for determining the optimal latency is crucial. In this paper, we introduce an integer linear programming (ILP)-based scheduling method to determine the optimal latency of iterative computing hardware. We consider the input-dependence of output accuracy of approximate hardware using data-driven error modeling for accurate quality estimation. The proposed method finds optimal or near-optimal latency with a significant speedup compared to exhaustive search and decision tree-based optimization. 
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